1. Field of the Invention
The present invention relates to semiconductor devices, and more specifically to a high efficiency MOS semiconductor device and to a process for manufacturing the same.
2. Description of Related Art
In electronic devices, such as those for radio frequency applications, the signals must be treated so as to prevent alteration of the same inside the device. Therefore, in the devices all the factors that can bring about a perturbation of the signal waveform or which can add noise to the signal must be minimized. Such factors, in the radio frequency devices, must be researched in the presence of the parasitic capacitances and in problems linked to the main physic-structural parameters, as the problem related to the power dissipation of the MOS technology device in the stationary state which is linked to the resistance of the device in the on state (Rdson). Thereby, there is the exigency of researching structural solutions to allow the achievement of both an optimization of such physic-structural parameters and a parasitic capacitance reduction.
The parasitic capacitance reduction of MOS technology semiconductor devices is linked to the use of the prefixed thickness of the field or gate oxide layers and of the dielectric layers. Such devices include active zones for treating the radio frequency signal and other electric signals which are necessary for the device's operation, and inactive zones assigned, for example, to the output and the input of the electric signals, such as the “gate-bus” and “gate-pad”. In such inactive zones, the main parasitic capacitance which must be reduced is represented by the gate-drain capacitance.
There is known the possibility of reducing such capacitance by forming shield regions (this is semiconductor regions doped with P-type dopant in the case of an N-channel MOS device) connected with the source terminal of the device, as shown in FIG. 1. In such figure, a final structure of a shielded pad is shown with a thick silicon oxide layer 11 (the even field oxide), a dielectric layer 12, a metal layer 13, and a passivation layer 14 only in the periphery parts of the structure. Such layers are placed over an N-type epitaxial layer 10 which constitutes the drain of the device and which is placed over a N-type substrate which is not shown.
In a central part A of the structure of FIG. 1, which constitutes the pad, the field oxide layer 11 has a lower thickness than in the periphery parts; this is due to the fact that, in the central part A, before the deposition of the dielectric layer 12, the field oxide layer 11 is attached and removed for providing an N-type dopant implant (typically there is used the same implant that allows the formation of a P-type semiconductor ring in the edge structure of the device). Successively, a thin silicon oxide layer 16 is formed in the central part A. After a P-type dopant diffusion, a P-type semiconductor well 15 is formed inside the N-type epitaxial layer and under the oxide layer of the central part, and the well is connected with the source terminal of the device.
In such a way, as shown in FIG. 2, the gate-drain capacitance Cgd is divided into a series of a gate-source capacitance Cgs due to the oxide layer and a drain-source differential capacitance Cds that changes according to the values of the potentials of the source and drain terminals. The capacitance Cgd changes essentially with the differential capacitance Cds when the source-drain voltage is not zero, while it depends principally on the capacitance Cgs when the source-drain voltage is zero. Since the capacitance Cgs is inversely proportional to the silicon oxide layer thickness, such capacitance will have a high value.